Generally, semiconductor memory devices for storing data are classified as either volatile semiconductor memory devices or nonvolatile semiconductor memory devices. Volatile semiconductor memory devices lose their data at power-off, while nonvolatile semiconductor memory devices maintain their data even without power. Because of their ability to store information in the absence of power, nonvolatile semiconductor memory devices have been widely used in applications where power may be interrupted suddenly.
A nonvolatile semiconductor memory device, such as a flash memory device, includes electrically erasable and programmable ROM cells, referred to as "flash EEPROM cells." Commonly, a flash EEPROM cell includes a cell transistor having a semiconductor substrate (or bulk) of a first conductive type (e.g., P-type), a source region and a drain region of a second conductive type (e.g., N-type) spaced apart from each other, a floating gate for storing charges placed over a channel region between the source and drain regions, and a control gate placed over the floating gate.
As known in the art, a flash memory device may contain a column-by-column array of NAND EEPROM cells having the general construction illustrated in cross-section by FIG. 11.58 and schematically by FIG. 11.59 in a handbook by B. Price et al., entitled Semiconductor Memories, John Wiley & Sons Ltd., pp. 603-604 (1991), incorporated herein by reference. A cross-sectional view showing the general construction of a column of NAND EEPROM cells and a corresponding schematic circuit diagram are provided in FIG. 3.
FIG. 1 is a block diagram illustrating the overall construction of a conventional flash memory device having the foregoing cell structure. Referring to FIG. 1, the conventional memory device 1 includes an array 10 divided into a plurality of memory blocks BLKm (where m=0-i). Each of the memory blocks BLK0-BLKi includes a plurality of memory cell strings, configured as illustrated in FIG. 2.
Referring to FIG. 2, each string is connected to a corresponding bit line BLn (where n=0-j), and has a string select transistor SST, a ground select transistor GST, and a plurality of flash EEPROM cell transistors M0 to M15 connected in series between a source of the string select transistor SST and a drain of the ground select transistor GST. A drain of the string select transistor SST in each string is connected to a corresponding bit line BLn, and a source of the ground select transistor GST therein is coupled to a common source line (or "common signal line") CSL. Gates of the string select transistors SST in the strings are connected in common to a string select line SSL, and gates of the ground select transistors GST therein are coupled in common to a ground select line GSL. Control gates of the flash EEPROM cell transistors M0-M15 in the strings are each coupled to a corresponding one of word lines WL0-WL15. The bit lines BL0-BLj are electrically connected to a sense amplifier circuit 16 (see FIG. 1). As is well known to ones skilled in the art, the sense amplifier circuit 16 of the NAND-type flash memory device is made up of a plurality of page buffers.
Returning to FIG. 1, the conventional NAND-type flash memory device 1 further comprises a row address buffer and decoder circuit 12, a column address buffer and decoder circuit 14, a Y-pass gate circuit 18, an input/output buffer circuit 20, a global buffer circuit 22, a command register 24, and a control logic and high voltage generator 26. The NAND-type flash memory device is disclosed in a data book, entitled "Flash Memory," published by SAMSUNG ELECTRONICS CO. Ltd., pp. 53-76, (March, 1998) (KM29U128T, 16MH8Bit NAND Flash Memory), incorporated herein by reference.
Referring to FIGS. 1 and 2, one of the memory blocks BLK0-BLKi is selected by a corresponding block decoder according to output signals from the row address buffer and decoder circuit 12. The lines SSL, WL0-WLi, and GSL of the selected memory block are supplied with drive voltages depending on a selected mode of operation, e.g., a program mode or a read mode. Data read out from the selected memory block is transferred to the I/0 buffer circuit 20 through the Y-pass gate circuit 18, which is controlled by the column address buffer and decoder circuit 14. And data to be written into the array 10 is transferred to the sense amplifier circuit 16 through the Y-pass gate circuit 18 and the I/O buffer circuit 20. Writing (comprising a program operation and an erase operation) and reading operations are controlled by the command register 24 and the control logic and high voltage generator 26.
FIG. 4A is a table showing bias conditions of memory cells according to each mode of operation, and FIG. 4B is a timing diagram illustrating signal levels during a programming operation according to the above-described flash memory device. Referring to FIGS. 4A and 4B, the program operation of the conventional flash memory device will now be more fully described with respect to two bit lines, i.e., BL0 and BL1.
As is well known in the art, during a program operation of a memory device, all of the memory cells that are connected to a selected row or a selected word line are simultaneously programmed. During programming, a word line WL1 in a selected memory block (e.g., BLK0) is selected, and the bit lines BL0 and BL1 are supplied with voltages based on data to be programmed into the memory cells. For example, in order to program data `1`, a bit line is supplied with a power supply voltage potential (e.g., Vcc). In order to program data `0`, on the other hand, a bit line is supplied with a ground voltage potential (e.g., GND).
As illustrated in FIGS. 4A and 4B, the selected word line WL1 is supplied with a positive high program voltage Vpgm, and unselected word lines WL0 and WL2 to WL15 are supplied with a positive pass voltage Vpass less than the program voltage Vpgm. The string select line SSL in the selected memory block BLK0 is supplied with a power supply voltage Vcc, and the ground select line GSL therein is supplied with the ground voltage GND. When a voltage of the selected word line WL1 transitions from GND to Vpgm and voltages of the unselected word lines WL0 and WL2 to WL15 transition from GND to Vpass, each channel of the respective strings corresponding to the bit lines BL0 and BL1 is boosted up to a predetermined program inhibit voltage Vpi by a capacitor coupling.
At this time, the string select transistor SST connected to the bit line BL1 is biased with Vcc applied to its gate, GND to its drain and Vpi to its source. Thus, the string select transistor SST is turned on, and the boosted program inhibit voltage Vpi of the channel is discharged to GND. A selected memory cell M1 (in the selected bit line BL1 and connected to the selected word line WL1) is programmed by F-N tunneling due to a voltage potential difference between its control gate and its drain and between its control gate and its source. That is, a substantial quantity of electrons are injected into the floating gate of the selected memory cell M1, and a threshold voltage of the cell M1 is shifted from a negative threshold voltage to a positive threshold voltage.
At the same time, however, the string select transistor SST connected to the non-selected bit line BL0 is biased with Vcc applied to its gate, Vcc to its drain and Vpi to its source. Thus, the string select transistor SST is turned off, and the boosted voltage Vpi of the channel is maintained (i.e., it is not discharged). A non-selected memory cell M1 (in the non-selected bit line BL0 and connected to the word line WL1) is program-inhibited because the potential difference sufficient to generate the F-N tunneling is not allowed to form between its control gate and its drain and between its control gate and its source. The memory cell M1 in the non-selected bit line BL0 is therefore maintained in a depletion-type transistor state, having a negative threshold voltage that represents an erased state.
As is also well known in the art, since a positive high pass voltage Vpass is applied to control gates of memory cells connected to unselected word lines WL0 and WL2 to WL15, the memory cells in the unselected word lines may be soft programmed. Soft programming is referred to as a "pass voltage (Vpass) stress" and influences program characteristics. The degree of being soft programmed, however, can be controlled so as not to affect overall programming characteristics. Since sixteen memory cells are arranged in each string, each memory cell in the string suffers the pass voltage stress as much as fifteen times. As the number of memory cells in a string is increased, each cell suffers more pass voltage stress.
The pass voltage stress can be mitigated by lowering a level of the pass voltage Vpass which is supplied to unselected word lines. As the pass voltage Vpass is lowered, however, the program inhibit voltage Vpi is also lowered. As noted previously, the program inhibit voltage Vpi is used to program inhibit non-selected memory cells. Accordingly, as the pass voltage Vpass is lowered, this means that the possibility of soft programming non-selected memory cells is also increased. Soft programming due to insufficient program inhibit voltages is referred to as a "program voltage (Vpgm) stress." Mitigation of the pass voltage stress therefore conflicts with mitigation of the program voltage stress.
In general, a block decoder to a memory block is laid out in a string pitch where memory cells in one string are arranged. Since the string pitch is continuously being reduced due to increased integration of memory cells, it is becoming more and more difficult to lay out the decoder in the string pitch. Conventionally, in order to lay out the decoder in the string pitch, the number of memory cells in a string has to be increased. Unfortunately, problems arise when the number of memory cells in the string is increased. One significant problem is that each memory cell in the string suffers an increased amount of pass voltage stress proportional to the increased number of memory cells in the string. Furthermore, since the number of word lines supplied with the pass voltage Vpass is increased, a pass voltage generator of larger capacitance is also required. The industry is therefore in need of a memory cell string array that permits an increase in the number of memory cells per string without increasing the pass voltage stress on each cell.